In today's computer systems, the speed of microprocessors has outstripped the speed of typical main memory DRAM systems. When a processor accesses main memory, the processor remains idle for a number of clock cycles, thus wasting precious time. In order to provide as many zero wait state memory accesses as possible, while maintaining a reasonable system cost, many of today's computer systems provide a high speed SRAM cache module. The faster and more expensive SRAM contains a subset of the slower and less expensive DRAM contents. The memory cache contains copies of data lines from main memory, each line including multiple bytes of data or program instructions (collectively referred to as "data").
When the microprocessor initiates a memory cycle (read or write), the cache module determines whether it contains a copy of a data line having data at the memory location specified by the microprocessor. If a copy resides in the cache (a cache hit), the microprocessor can achieve a zero wait state memory access. If a copy does not reside in the cache (a cache miss), a main memory access occurs, and the microprocessor remains idle for a number of clock cycles. As the processor operates, the cache contents are regularly changed to include copies of memory lines recently requested by the microprocessor (temporal locality) and to include memory lines in memory locations consecutive to those recently requested (spatial locality).
In the case of a write operation to a memory location having data copied in the cache (a cache write hit), the cache memory is updated, and main memory is then said to contain stale information. The cache line is said to be modified, or dirty, because it is no longer a duplicate of the corresponding line in memory. If main memory is not updated and another bus master (such as a DMA or SCSI controller) accesses main memory, data consistency/coherency problems may result.
Variations on two distinct write policies are employed to prevent data coherency problems. One is called a write-through policy, in which the cache immediately passes each write operation initiated by the microprocessor through to main memory. Even in the case of a cache write hit, both the cache line and the corresponding line in main memory are updated, thereby ensuring consistency between the cache and main memory. The write-through policy is simple to implement, but has the performance limitations associated with each write operation requiring access to the slow main memory.
A second write policy is called a write-back policy, in which main memory is updated only when necessary. This keeps the system bus free for use by other bus masters and is particularly advantageous when significant system I/O activity is expected. Main memory is updated when (1) a bus master other than the microprocessor initiates a read access to a memory line which contains stale data; (2) a bus master other than the microprocessor initiates a write access to a memory line which contains stale data; and (3) a modified cache line is about to be overwritten to store a copy of a memory line newly requested by the microprocessor. When a bus master other than the microprocessor initiates a memory cycle, the cache module must monitor, or snoop, the system bus to check for memory accesses to lines marked as modified in the cache.
Many of today's microprocessors include an SRAM cache internal to the microprocessor chip. Such a cache is called an L1 cache. Computer system designers may still provide a supplementary external cache, called an L2 cache, to further increase system performance. Maintaining coherency amongst the various caches and main memory is correspondingly more complex than for the exemplary single cache system discussed above, particularly when one or more of the caches employs a write-back policy.
It is oftentimes desirable to allow an end user or manufacturer to decide whether to include the external L2 cache as an upgrade to the computer system. In such a case, the system designer provides a connector for an optional cache module. This reduces manufacturing costs, since a single system board can be used for computer systems with or without an external L2 cache. However, the various control signals necessary to maintain cache coherency must then be routed differently, depending on whether the optional L2 cache module is included. Currently, the alternative routing of the control signals is accomplished with jumpers, which must be physically connected according to whether the L2 cache module upgrade is included. The use of jumpers can be quite inconvenient, particularly for an end user of modest technical sophistication.